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Advancing system-level verification using UVM in SystemC

 
: Barnasconi, Martin; Pêcheux, François; Vörtler, Thilo

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DVCon 2014, Design and Verification Conference and Exhibition. Proceedings. Online resource : 03. - 06. March 2014, San Jose
2014
Session 1, 18 pp.
Design and Verification Conference and Exhibition (DVCon) <2014, San Jose/Calif.>
European Commission EC
FP7-ICT; 287562; VERDI
English
Conference Paper, Electronic Publication
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
Electronic System Level (ESL); Hardware-in-the-Loop (HiL); Rapid Control Prototyping (RCP); SystemC; SystemC Verification (SCV); Transaction Level Modeling (TLM); Universal Verification Methodology (UVM)

Abstract
This paper introduces the Universal Verification Methodology (UVM) using SystemC and C++ (UVM-SystemC), to advance system-level verification practices. UVM-SystemC enables the creation of a structured, modular, configurable and reusable test bench environment. Unlike other initiatives to create UVM in SystemC, the presented proof-of-concept class library uses identical constructs as defined in the UVM standard for test and sequence creation, verification component and test bench configuration and execution by means of simulation. Users familiar with either SystemC and/or with UVM will immediately feel comfortable to start using UVM-SystemC right away. The Universal Verification Methodology becomes universal, at last.

: http://publica.fraunhofer.de/documents/N-287075.html