Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

GaN HEMT and MMIC development at Fraunhofer IAF: Performance and reliability

: Waltereit, P.; Bronner, W.; Quay, R.; Dammann, M.; Kiefer, R.; Müller, S.; Musser, M.; Kühn, J.; Raay, F. van; Seelmann-Eggebert, M.; Mikulla, M.; Ambacher, O.; Rijs, F. van; Rödle, T.; Riepe, K.


Physica status solidi. A 206 (2009), No.6, pp.1215-1220
ISSN: 0031-8965
ISSN: 1862-6300
ISSN: 1521-396X
ISSN: 1862-6319
Journal Article
Fraunhofer IAF ()

We present a systematic study of epitaxial growth, processing technology, device performance and reliability of our GaN HEMTs and MMICs manufactured on 3 inch SiC substrates. Epitaxy and processing are optimized for both performance and reliability. The deposition of the AlGaN/GaN HEMT epitaxial structures is designed for low background carrier concentration and a low trap density in order to simultaneously achieve a high buffer isolation and low DC to RF dispersion. Device fabrication is performed using standard processing techniques involving both electron-beam and stepper lithography. Gate lengths of 250 nm and 500 nm are employed for 10 GHz and 2 GHz applications, respectively. The developed HEMTs demonstrate excellent high-voltage stability, high power performance and large power added efficiencies. Devices exhibit two-terminal gate-drain breakdown voltages in excess of 160 V (current criterion 1 mA/mm) across the entire 3 inch wafer with parasitic gate and drain Currents well below 1 mA/mm when biased up to 80 V drain bias under pinch-off conditions. Load-Pull measurements at 2 GHz on 800 pm gate width devices return a well-behaved relationship be-tween bias-voltage and output-power as well as power-added-efficiencies beyond 60% up to U-DS = 100 V. For a drain bias of 100 V an output-power-density around 22 W/mm with 26 dB linear gain is obtained. On large devices (32 mm ate width packaged in industry-standard ceramic packages) an output power beyond 100 W is achieved with a PAE above 50% and a linear gain around 15 dB. Dual-stage MMICs in microstrip transmission line technology yield a power added efficiency of 40% at 8.56 GHz for a power level of I I W. A single-stage MMIC yields a PAE of 46% with 7 W of output power at V-DS = 28 V. Reliability is tested on HEMT devices having a gate periphery of 8 x 60 pin as an operating bias of 50 V under both DC and RF conditions. About 10% drain-current change under DC-stress (50 mA/mm) is observed after more than 1000 h of operation with an extrapolated drain-current degradation below 20% after 200000 h (more than 20 years) of operation. Under RF stress (2 GHz, I dB compression) the observed change in output power density is below 0.2 dB after more than 1000 It.