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Runtime adaptive multi-processor system-on-chip: RAMPSoC

: Göhringer, D.; Hübner, M.; Schatz, V.; Becker, J.

Fulltext urn:nbn:de:0011-n-972668 (652 KByte PDF)
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Created on: 19.9.2009

Institute of Electrical and Electronics Engineers -IEEE-; IEEE Computer Society, Technical Committee on Parallel Processing:
IEEE International Symposium on Parallel & Distributed Processing, IPDPS 2008 : Miami, FL, 14 - 18 April 2008
Piscataway, NJ: IEEE, 2008
ISBN: 978-1-4244-1693-6
ISBN: 978-1-4244-1694-3
7 pp.
International Symposium on Parallel & Distributed Processing (IPDPS) <22, 2008, Miami/Fla.>
Conference Paper, Electronic Publication
Fraunhofer FOM ( IOSB)
multiprocessor system; reconfigurable hardware; FPGA; run-time adaptive system

Current trends in high performance computing show, that the usage of multiprocessor systems on chip are one approach for the requirements of computing intensive applications. The multiprocessor system on chip (MPSoC) approaches often provide a static and homogeneous infrastructure of networked microprocessor on the chip die. A novel idea in this research area is to introduce the dynamic adaptivity of reconfigurable hardware in order to provide a flexible heterogeneous set of processing elements during run-time. This extension of the MPSoC idea by introducing run-time reconfiguration delivers a new degree of freedom for system design as well as for the optimized distribution of computing tasks to the adapted processing cells on the architecture related to the changing application requirements. The "computing in time and space" paradigm and the extension with the new degree of freedom for MPSoCs will be presented with the RAMPSoC approach described in this paper.