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Gate-level digital power simulation with varying technology parameters

: Eichler, U.; Haase, J.; Häußler, R.; Kinzelbach, H.

Fulltext urn:nbn:de:0011-n-747202 (291 KByte PDF)
MD5 Fingerprint: a76c829772ab91bad6099494884641a2
Created on: 3.9.2008

Schmidt, G.:
SCD 2008, Semiconductor Conference Dresden 2008. Workshop-CD : International Conference, Workshop and Exhibition on Chip, Packaging, Design, Simulation and Test. 23. - 24. April 2008, Dresden
Martinsried: Gerotron Communication, 2008
4 pp.
Semiconductor Conference Dresden (SCD) <2008, Dresden>
Conference Paper, Electronic Publication
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Today, power consumption plays an important role in digital IC design. Demands come from the application side regarding battery life time of mobile devices and also from technology side where below 90 nanometers the heat density of complex ICs is a major problem and can even become larger than that of a stove top. Variations in the semiconductor production process can have a significant influence on the power consumption of an IC. To consider these effects in the design flow, a statistical simulation is needed. While at spice level it is still possible to map the statistical properties of varying transistor parameters to timing and power measures of single cells, this abstraction is much more difficult to find for whole digital designs. As an alternative this paper presents a Monte-Carlo gate-level simulation approach for statistical timing and power analysis based on process parameter sensitivity information. After a brief explanationof the basic approach the proposed design flow and some implementation details are described. First simulation results are presented using a small example design.