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Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems

: Hübner, M.; Braun, L.; Göhringer, D.; Becker, J.

Fulltext urn:nbn:de:0011-n-1005381 (PDF)
MD5 Fingerprint: b51177071a5803f4bfc68f1d5307462e
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Created on: 19.9.2009

Institute of Electrical and Electronics Engineers -IEEE-; IEEE Computer Society, Technical Committee on Parallel Processing:
IEEE International Symposium on Parallel & Distributed Processing, IPDPS 2008 : Miami, FL, 14 - 18 April 2008
Piscataway, NJ: IEEE, 2008
ISBN: 978-1-4244-1693-6
ISBN: 978-1-4244-1694-3
6 pp.
International Symposium on Parallel & Distributed Processing (IPDPS) <22, 2008, Miami/Fla.>
Conference Paper, Electronic Publication
Fraunhofer FOM ( IOSB)

Since the 1990s reusable functional blocks, well known as IP-Cores, were integrated on one silicon die. These Systems-on-Chip (SoC) used a bus-based system for intermodule communication. Technology and flexibility issues forced to introduce a novel communication system called Network-on-Chip (NoC). Around 1999 this method was introduced and until then it is investigated by several research groups with the aim to connect different IP-Blocks through an effective, flexible and scalable communication network. Exploiting the flexibility of FPGAs, the run-time adaptivity through run-time reconfiguration, opens a new area of research by considering dynamic and partial reconfiguration. This paper presents an approach for exploiting dynamic and partial reconfiguration with Xilinx Virtex-II FPGAs for a multi-layer Network-on-Chip and the related techniques for adapting the network while run-time to the requirements of an application.