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New dimensions for multiprocessor architectures

On demand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach
: Göhringer, D.; Hübner, M.; Perschke, T.; Becker, J.

Fulltext urn:nbn:de:0011-n-1005296 (387 KByte PDF)
MD5 Fingerprint: a81c17c315bd18892904bfe5d108ad19
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Created on: 19.9.2009

Kebschull, U. ; Institute of Electrical and Electronics Engineers -IEEE-:
International Conference on Field Programmable and Logic Applications 2008. Vol.2 : Heidelberg, Germany, 8 - 10 September 2008
Piscataway, NJ: IEEE, 2008
ISBN: 978-1-4244-1960-9
ISBN: 978-1-4244-1961-6
International Conference on Field Programmable and Logic Applications (FPL) <18, 2008, Heidelberg>
Conference Paper, Electronic Publication
Fraunhofer FOM ( IOSB)
MPSoC; reconfigurable hardware; image processing

Multiprocessor hardware architectures enable to distribute tasks of an application to several microprocessors, in order to exploit parallelism for accelerating the performance of computation. Especially for the application domain of image data processing, where computation performance is a crucial factor to keep the real-time requirements, this approach is a promising solution for the assembly of high sophisticated algorithms e.g. for object tracking. Changing requirements and the necessary implementation of the tasks in terms of modified algorithms, precision and communication needs to be handled by software and hardware adaptation in state of the art architectures. Field Programmable Gate Arrays (FPGAs) enable to exploit the adaptation of hardware cores and the software running on embedded microprocessor cores on an integrated multiprocessor system.