Forschungsfabrik/Verbund Mikroelektronik

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  • Publication
    Terahertz technologies for non destructive testing
    ( 2023)
    Nüßler, Dirk
    ;
    Grimm, Andreas
    ;
    Heinrich, Wolfgang
    ;
    Chartier, Sébastien
    ;
    Fischer, Gunter
    ;
    Friederich, Fabian
    Inline measurement systems in the terahertz range offer the potential to become an important part of quality assurance in the longer term. Despite the undisputed advantages in terms of contrast, sensitivity, measurement speed and resolution, there is a lack of suitable chip technologies for implementation. In the T-KOS project, a first basis for future terahertz line cameras was developed and verified.
  • Publication
    Chiplets - Exploring the Green Potential of Advanced Multi-Chip Packages
    ( 2020)
    Nissen, Nils F.
    ;
    Clemm, Christian
    ;
    Billaud, Mathilde
    ;
    Töpper, Michael
    ;
    Stobbe, Lutz
    ;
    Schneider-Ramelow, Martin
    In addition to already widely applied multi-chip packages, a new wave of IC packaging integration is currently taking place. The concepts and first implementations of chiplets promise not only higher integration densities, but also touch upon environmental properties of electronics in terms of resource efficiency, critical raw materials, modularity and re-usability of design blocks. This paper presents examples of chiplets and variations of the concept in comparison to earlier multi-chip packages. Many variants of multi-chip packages are already commonly included in smartphones. Therefore, in the context of environmental assessments, it is highly relevant to use suitable IC data sets instead of generic single-chip package data sets. Unless individual data sets for all IC types become the norm throughout the electronics industry, a configurable calculation model is needed to improve the quality of many environmental assessments.
  • Patent
    Klebeverfahren zum Verbinden zweier Wafer
    ( 2017)
    Zoschke, Kai
    ;
    Töpper, Michael
    Die vorliegende Anmeldung umfasst ein Klebeverfahren zum Verbinden eines ersten Wafers (101) und eines zweiten Wafers (401; 501), wobei zunächst eine erste Klebeschicht (102) auf eine Oberfläche des ersten Wafers (101) aufgetragen wird. Weiterhin wird eine zweite Klebeschicht (201) auf die erste Klebeschicht (102) aufgetragen und die beiden Klebeschichten (301, 302) werden durch selektives Entfernen beider Klebeschichten in mindestens einem vorgegeben Bereich des ersten Wafers (101) strukturiert. Weiterhin wird der erste Wafer (101) mit dem zweiten Wafer (401; 501) durch Drücken einer Oberfläche des zweiten Wafers (401; 501) auf die zweite Klebeschicht (302) verbunden, wobei die zweite Klebeschicht (302) beim Verbinden des ersten Wafers (101) mit dem zweiten Wafer (401; 501) fließfähiger als die erste Klebeschicht (301) ist.
  • Publication
    Glass based interposers for RF applications up to 100GHz
    ( 2016)
    Woehrmann, Markus
    ;
    Juergensen, Nils
    ;
    Lutz, Mario
    ;
    Wilke, Martin
    ;
    Duan, Xiaomin
    ;
    Ndip, Ivan
    ;
    Töpper, Michael
    ;
    Lang, Klaus-Dieter
    Glass is well established as wafer or panel substrate for applications like capping of image sensors or as low loss carrier for integrated passive devices. Glass substrates with higher functionality becomes more attractive for the advanced packaging due the improvement of glass processing and the increased implementation of photonic packaging which is demanded for higher data transfer rates. The through glass vias are therefore essential for the SiP and 3-D integration.
  • Publication
    Wafer level chip scale packaging
    ( 2016)
    Töpper, Michael
    Wafer level chip scale packaging (WL-CSP) based on redistribution is the key technology which is evolving to system in package (SiP) and heterogeneous integration (HI) extended by 3-D packaging using through silicon vias (TSV). Due to further miniaturization on the chip-level WLP (wafer level package), it has been expanded to FO-WLP (fan-out WLP) which uses a molding process to expand the die size for redistribution. Therefore, the original WLP process for WL-CSP using redistribution is now called FI-WLP (fan-in WLP). Materials and process technologies are key for a reliable WLP. It is not only the choice for the right polymer or metal but the interfaces could be even more critical like under bump metallurgy or the adhesion of polymers. This chapter focuses on the materials and processes for WLP which are the basic for most of all new 3-D integration technologies.
  • Publication
    Material and process trends for moving from FOWLP to FOPLP
    ( 2015)
    Braun, Tanja
    ;
    Voges, S.
    ;
    Töpper, Michael
    ;
    Wilke, Martin
    ;
    Wöhrmann, M.
    ;
    Maaß, Uwe
    ;
    Huhn, Max
    ;
    Becker, Karl-Friedrich
    ;
    Raatz, Stefan
    ;
    Kim, J.-U.
    ;
    Aschenbrenner, Rolf
    ;
    Lang, Klaus-Dieter
    ;
    O'Connor, C.
    ;
    Barr, R.
    ;
    Calvert, J.
    ;
    Gallagher, M.
    ;
    Iagodkine, E.
    ;
    Aoude, T.
    ;
    Politis, A.
    Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. The technology offers not only solutions for single chip packaging but also approaches for 3D system integration or RF suitable packaging. Mold embedding for this technology is currently done on wafer level up to 12"/300 mm size. For higher productivity and therewith lower costs larger mold embedding form factors are forecasted for the near future. Besides increasing wafer sizes up to 450 mm an alternative option would be moving to panel sizes leading to Fan-out Panel Level Packaging (FOPLP). Sizes for the panel could range up to 18"x24" or even larger. Increasing the embedding size does not only mean an upscaling of the existing technologies but may lead to a change from using wafer processing infrastructure to the ones used for panels. This is especially true when moving from round wafer sizes to larger rectangular panel formats. Here also new materials and processes have to be taken into account. Materials for reconfigured mold embedding as well as dielectric materials for electrical wiring redistribution are key factors for reliable packaging and proven functionality as required e.g. for RF packaging. For reconfigured mold embedding, compression mold processes are used in combination with liquid, granular or sheet compound. Within this paper the evaluation of panel level compression molding with a target form factor of 24"x18" / 610x457 mm² is described for different materials. As basis for the redistribution on top of the mold embedded wafer typically a liquid photo-patternable dielectric polymer material is used and applied by spin coating. For large panel sizes photo-patternable materials are still of interest, these will most likely be used as dry films. These are expected to have advantages concerning processing and cost compared to liquid dielectric materials. Hence, a dry film dielectric material has been selected and evaluated for Fan-out Wafer/Panel Level Packaging. The main criterion for the selection of the thin film polymers is the curing temperature due to the fact that the final polymerization has to be done after the deposition on the molded wafer. Standard PIs and PBOs can therefore not be used because temperatures above 250 °C would damage the molding material. BCB-type materials are below this temperature limit, with cure temperatures as low as 200°C, making them ideal candidates for FOWLP. In addition the electrical properties are paving the way to RF applications. However, regarding the RF performance the inhomogeneous material mix of the package can be a critical issue, because of complex wave propagation phenomena. In order to obtain a proper design an assessment of the RF properties is therefore essential. For material and process evaluation a test vehicle has been designed with focus on material and process evaluation as well as reliability testing. In addition test structures for basic RF characterization have been designed and integrated. The test structures comprise interconnect elements such as transmission lines (TML) and vias to assess the electrical performance of FOWLP packaged ICs. Single ended coplanar and differential ended transmission lines embedded into the BCB-based dry film dielectric are connected by vias with a specifically designed silicon IC. The design was done using 3D full-wave simulations. An analysis of the RF characteristics shows low insertion loss and good return loss characteristics up to frequencies of 40 GHz. In summary this paper describes material and process trends for Fan-out packaging when moving from wafer sizes to large panel formats.
  • Publication
    Impact of RDL Polymer on Reliability of Flip Chip Interconnects in Thermal Cycling - Correlation of Experiments with Finite Element Simulations
    ( 2014)
    Müller, Matthias
    ;
    Wöhrmann, Markus
    ;
    Wittler, Olaf
    ;
    Bader, Volker
    ;
    Töpper, Michael
    ;
    Lang, Klaus-Dieter
    For WLP (Wafer Level Packaging) thin film polymers play a key role in respect to board level reliability. This paper introduces a reliability indicator giving a tendency of the polymer material to crack initiation around the UBM pad. This indicator derived from Finite Element simulated maximum stress in polymer layer and the material specific tensile strength. Comparing the simulation results with the experimental data we see the same impact of the mechanical material properties on the reliability. This proves the described reliability indicator as suitable for estimating thermal cycle reliability of RDL polymer materials gives application engineers and manufacturers a new tool for selecting the most suitable RDL material for e.g. flip chip and WLP applications.
  • Publication
    Development of a high density glass interposer based on wafer level packaging technologies
    ( 2014)
    Töpper, Michael
    ;
    Wöhrmann, Markus
    ;
    Brusberg, Lars
    ;
    Jürgensen, Nils
    ;
    Ndip, Ivan
    ;
    Lang, Klaus-Dieter
    Currently glass is mainly used as unstructured wafers or panels with the highest market share in glass capping applications. Higher functionality in glass is driven by the applications in RF and Photonics. Since the technologies of via interconnects in Si and glass are completely different, it is challenging to perform a direct and fair comparison. Mainly laser technology and electrical discharge are used for forming the vias into the glass. Slightly modified thin film technologies already in mass production in WLP can be used to fill the vias with a copper metallization. Conformal metallization and full via plating are options. High yield and excellent reliability have been achieved. Generally, due to the lossy nature of silicon and complex polarization mechanism that occurs at the Si-SiO2, TSVs may suffer from severe signal integrity and EMI problems such as huge insertion loss, delay and cross-talk, depending on the Si-resistivity considered. Therefore, regarding the dielectric material, TGVs have significant advantages over TSV, especially when either LRS or MRS is used. In summary TGVs show excellent RF characteristics over TSVs. This has been proven for a test design up to 40 GHz.
  • Publication
    Korrosionsphänomene im mikroelektronischen System
    ( 2014)
    Wagner, Stefan
    ;
    Höppner, Katrin
    ;
    Töpper, Michael
    ;
    Wittler, Olaf
    ;
    Lang, Klaus-Dieter
    Der Einfluss von korrosiven Phänomenen auf mikroelektronischen Systemen ist einer der kritischsten Effekte im Hinblick auf die Langzeitbeständigkeit. Beschleunigte Zuverlässigkeitstests berücksichtigen diese Problematik nur unzureichend. Systeme für den Bereich ,Power Elektronik? sind durch die hochkritischen und zum Teil extremen Umgebungsbedingungen besonders gefordert. Als Schutzmaßnahme nutzt man oft polymere Schutzverkapselungen. Diese sind zwar nicht hermetisch, bieten aber einen guten Kompromiss zwischen Systemgröße und Kosten für die Mehrzahl der Anwendungen. Problematisch ist hierbei die Permeabilität der Polymere, die den Zugang von Feuchte und auch korrosiv wirkenden Gasen in das Gehäuse erlauben, somit die elektronischen Funktionsstrukturen auf dem Chip, die Bond-Drähte und -Flächen, die Leadframes und gar die Lotkontakte schädigen können. Korrosion ist somit ein besonders für die Langzeitbeständigkeit persistentes Problem und kann nur aus Systemsicht angegangen werden. Hier wird nun versucht die korrosionsinduzierte Degradation von mikroelektronischen Gehäusen in einer Übersicht darzustellen und Messverfahren zum Nachweis der Schutzeignung von Verkapselungslagen unter Nutzung elektrochemischer Messtechniken darzulegen.
  • Publication
    Characterization of thin polymer films with the focus on lateral stress and mechanical properties and their relevance to microelectronics
    ( 2014)
    Wöhrmann, Markus
    ;
    Fischer, Thorsten
    ;
    Walter, Hans
    ;
    Töpper, Michael
    ;
    Lang, Klaus-Dieter
    Thin film polymers play an essential role in system integration. The mechanical properties of the polymers are crucial for 3-D-Integration and advanced WLP because with the thinning of the silicon wafers, i.e. chips to less than 150 mm, the influence of the polymer layers gets an increasing impact on the mechanical stability of the electronic device. Next generation polymers have entered the market which are tailored to reach the further optimized mechanical property parameter set. This paper will give a guideline for the choice of the optimal polymer based on the demands of the application in relation to the material properties. The main material properties for high reliability are the Young's modulus, tensile strength, elongation at break and coefficient of thermal expansion. Aside of the material properties of the polymer the interaction of the polymer layer with the substrate is important. The material mismatch causes for example warpage and material cracking; the main impact factor being the residual stress in the layers in relation to the fracture toughness of the material and the interface. The warpage is an issue for the processing and the assembly process. The focus of our investigation is on properties of polymers on silicon substrates. The development of stresses in the polymer layers is measured and analyzed for different polymers (BCB, PI, PBO). The residual stress in a thin polymer film is measured by the warpage of the substrate in relation to different temperatures depending on the application. The estimation of stress-temperature behavior allows to develop processing concepts for a stress reduction being essential for 3-D integration. The generated stress drives cracking which leads to the effect that the impact of the forces should be taken into account for the quantification of the fracture toughness. The relation between the stress as the driving force and the fracture toughness are further discussed in details. A comprehensive study of- the mechanical polymer properties is essential for high reliable devices.