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Defect monitoring and layout related yield and reliability prediction for VLSI interconnects

 
: Dreizner, A.; Lukat, Klaus; Pahlitzsch, J.; Kück, H.

Brydon, G.M.:
ESREF '94. Proceedings of the European Symposium on Reliability of Electron Devices, Failure Physics and Analysis
Glasgow, 1994
S.143-146
European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF) <5, 1994, Glasgow>
Englisch
Konferenzbeitrag
Fraunhofer IMS, Außenstelle Dresden ( IPMS) ()
Ausbeute; Ausfallhäufigkeit; Elektromigration; layout; Leiterbahn; Zuverlässigkeit

Abstract
Based on in-process defect monitor data and layout related Monte Carlo calculations we predict the yield of IC metal layers and the probability that missing metal defects reduce the IC reliability. the influence of such defects on electromigration failure distributions is investigated by experiments on submicron test structures.

: http://publica.fraunhofer.de/dokumente/PX-9077.html