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A comparison of flip chip technology with chip size packages

: Simon, J.; Töpper, M.; Reichl, H.; Chmiel, G.

International Electronics Packaging Society -IEPS-:
International Electronics Packaging Conference 1995. Proceedings : September 24 - 27, 1995, Sheraton on Harbor Island Resort, San Diego, California
Wheaton, Ill.: International Electronics Packaging Society, 1995
ISBN: 1-88043-317-6
International Electronics Packaging Conference <1995, San Diego/Calif.>
Fraunhofer IZM ()

The advantages of flip chip technology concerning electrical performance and smallest mounting area are well-known. Unfortunately most of the available dice are not designed for flip chip application with an area arrangement of the bond pads. At least for the immediate future it must be assumed that the majority of integrated circuits will be used in packages and therefore will have peripheral bondpads. If the die size is determinded by the peripheral bondpads, shrinking of the size requires reducing the pitch. A reduced pitch may limit the use as a flip chip. Hence Chip Size Packages (CSP) offer a solution of this problem. The CSP allows matching the fine peripheral pitch to an area arrangement with increased pitch. The additional packaging level of the CSP gives several advantages: the rewiring allows a standardization. The standardization is benefical for standarized testequipment, e.g. for burn-in. Therefore the CSP will become an alternative to the KGD as the CSP will approximately have the same dimension as the bare die. To demonstrate the benefits of the CSP a FC-BGA was developed on wafer level. The FC-BGA uses multilayer and bumping technologies for rewiring the peripheral bondpads to an area array. A die with 328 I/O's and a peripheral pitch of 100µm was used as a testsample. Rewiring resulted in a pitch of 350µm, which is suitable for PCB.