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Verfahren und Schaltungsanordnung zum zeitlichen Regenerieren von NRZ-Signalen im Gbit/s-Bereich

Retiming circuit for high speed data transmission - in which pulse edges are separated and recombined by flip-flop action to maintain transmission in giga-bit-per-second range.
: Enning, B.

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DE 1980-3028714 A: 19800725
DE 1980-3028714 A: 19800725
DE 3028714 A1: 19820304
Patent, Elektronische Publikation
Fraunhofer HHI ()

DE 3028714 A UPAB: 19930915 The object of the circuit is to provide a retiming system for data transmission in the GBit/sec range for non-return to zero (NRZ) signals. At lower frequencies, a D-type flip-flop is used for this purpose, but due to feedback delays this is limited to operation at about 600MHz. The circuit is in fact a reset-set flip-flop which has the attwibutes of a D-type flip-flop. The NRZ signal is sampled at its bit rate in a three transistor circuit (T1,T2,T3). The signal is applied to one base (1), the bit rate pulse to another (2) and a reference voltage to the third (T2). The result is a series of return to zero (RZ) pulses of one polarity which are then also inverted in a pnp-transistor cascade (T4,T5). Both polarities arrive at a summing junction (S) via time delays (t1,t2) and damping elements (D1,D2). The summed bipolar signal is applied to a Schmitt trigger circuit (T6,T7) acting as a differential amplifier with feedback, at whose output (3) the NRZ signal is replicated in cleaned up form. The feedback delay can be adjusted by a capacitor (C1). The choice of transistor type assists in preventing internal oscillations, and the almost complete absence of internal feedback loops allows operation at the required frequency.