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1991
Conference Paper
Titel
An architecture for a high performance programmable rendering engine
Abstract
We present an architecture for a hogh-performance programmable rendering engine. This chip or chip-set will be able to deliver one Gouraud-shaded, z-buffered, texture-modulated and alphablended pixel every clock cycle. Focus of the paper is the derivation of the architecture of the pixel processing block from the applied algorithms. (IGD)
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