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An architecture for a high performance programmable rendering engine

 
: Ackermann, H.-J.; Hornung, C.

Eurographics Hardware Workshop '91. Proceedings
1991
Eurographics Hardware Workshop <1991>
Englisch
Konferenzbeitrag
Fraunhofer IGD ()
Algorithmen; high performance; texture models; Z-buffering

Abstract
We present an architecture for a hogh-performance programmable rendering engine. This chip or chip-set will be able to deliver one Gouraud-shaded, z-buffered, texture-modulated and alphablended pixel every clock cycle. Focus of the paper is the derivation of the architecture of the pixel processing block from the applied algorithms. (IGD)

: http://publica.fraunhofer.de/dokumente/PX-4589.html