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Three dimensional metallization for vertically integrated circuits



Microelectronic engineering 37/38 (1997), S.39-47 : Lit.
ISSN: 0167-9317
European Workshop on Materials for Advanced Metallization (MAM) <2, 1997, Villard de Lans>
Fraunhofer IFT; 2000 dem IZM eingegliedert
CMOS integrated circuits; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; wafer bonding

Mainstream planar technology is marked by physical and technological limitations which have a severe impact on system characteristics. The performance, multi-functionality and reliability of microelectronic systems are mainly limited by the wiring between the ICs and subsystems. The "on-chip" wiring also leads to a critical performance bottleneck for future IC generations which can be solved only temporarily by the introduction of additional metallization layers and innovative materials (copper, low- epsilon dielectrics). 3D IC fabrication creates a basis to overcome these drawbacks and to pave the way for system approaches of an entirely new quality. We realized a three dimensional metallization for vertically integrated circuits (VIC) using a newly developed technology that allows stacking and vertical interchip wiring of completely processed and electrically tested wafers using available microelectronic processes. Wafers are stacked using an aligned bonding process. Vertical electri cal connections are formed between the uppermost metal levels of the bonded wafers by fabrication and metal refill of high aspect ratio interchip vias. This interchip via (ICV) concept allows the formation of multiple wafer stacks using CMOS compatible materials and process steps exclusively and avoids wafer back processes. The potential of the ICV technology is the realization of some 100000 vertical interconnects per cm2 with 1-4 mu m2 arbitrarily selectable interchip vias.