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Quality and yield of ultra fine pitch stencil printing for flip chip assembly

 

Deutscher Verband für Schweißtechnik e.V. -DVS-, Düsseldorf:
EuPac '98. 3rd European Conference on Electronic Packaging Technology & 9th International Conference on Interconnection Technology in Electronics. Lectures and poster
Düsseldorf: DVS-Verlag, 1998 (DVS-Berichte 191)
ISBN: 3-87155-497-9
S.32-36
European Conference on Electronic Packaging Technology (EuPac) <3, 1998, Nürnberg>
International Conference on Interconnection Technology in Electronics <9, 1998, Nürnberg>
Englisch
Konferenzbeitrag
Fraunhofer IZM ()
circuit layout CAD; fine-pitch technology; flip-chip devices; integrated circuit interconnections; integrated circuit metallisation; integrated circuit packaging; integrated circuit yield; microassembling; quality control; software tools; Soldering

Abstract
Stencil printing for SMT and fine pitch BGA structures is established as a low cost standard process. Using the same equipment with modified printing parameters and materials, a low cost bumping process has been transferred to serial production. This paper presents the results of ultra fine pitch stencil printing of solder paste on wafers (down to 200 mu m and 150 mu m pitch) with regard to quality and yield. A software tool for design of the stencil layout was developed and the predicted bump heights were compared to the experimental results. In the first part of the paper, a low cost bumping method for flip chip technology is described in detail. This technology is based on chemical Ni/Au deposition on wafers. For solder bumping on wafers, the key aspects of solder paste printing with optimized printable apertures are described and the printing results are presented. The second part of this paper is a comparison of measured standard deviations of bump heights and the quality demands for ultra fine pitch flip chip assembly.

: http://publica.fraunhofer.de/dokumente/PX-30582.html