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Precision Tin/Lead Alloy Plating for Flip-chip Mounting Technology

 
: Richter, H.; Rueß, K.; Gemmler, A.; Leonhard, W.

Microelectronics international (1997), Nr.42, S.9-13, 19
ISSN: 1356-5362
Englisch
Zeitschriftenaufsatz
Fraunhofer IPA ()
Beschichten; Drahtbondtechnik; elektrochemische Beschichtung; Flip-Chip-Montagetechnik; Flip-Chip-Technik; Galvanisieren; Halbleiter; Legierung; Metallbeschichtung; Microplating; Präzisionsgalvanik; Schutzschicht; Solder-Bump-Technologie; Soldering; Spanen; Tin/Lead alloy; Tin/lead alloy plating; wafer; wafer bumping; Zinn/Blei-Legierung; Zinnbleilot

Abstract
Bumping is a prerequisite for flip-chip attachment of bare dies. For silicon semiconductors bumping is normally performed on the ICs at wafer scale. Bumping can be performed by micro-plating or vacuum deposition techniques. Mechanical methods are also well-known. In this paper a bumping process based on tin/lead alloy plating is reported. The plating bath presented enables the deposition of both solder composition used for flip-chip attachment, the eutetic and the lead-rich. All key issues of the plating process covering plating equipment, electrolyte characteristics and plating process parameters are discussed. Methods of bump characterisation and quality assurance are reported as an important part of the bumping process. The deciding process parameters leading to high quality solder bumps are demonstrated.

: http://publica.fraunhofer.de/dokumente/PX-29198.html