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20 Gbit/s 2 to 1 multiplexer using 0.3 mym gate length double pulse doped Quantum Well GaAs/AlGaAs transistors.

20 Gbit/s 2 zu 1 Multiplexer unter Verwendung von Doppel Puls dotiertem Quantum Well GaAs/AlGaAs Transistoren mit einer Gate-Länge von 0.3 mym
 

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Microelectronic engineering 15 (1991), S.323-326 : Abb.,Lit.
ISSN: 0167-9317
Englisch
Zeitschriftenaufsatz
Fraunhofer IAF ()
communication system; E/D Transistor; high-speed switch; Hochgeschwindigkeitsschalter; Kommunikationssystem; multiplexer; source coupled fet logic; test equipment instrumentation; Testgerät

Abstract
A high speed 2:1 multiplexer circuit in source coupled FET logic has been developed and fabricated using a recessed gate process for enhancement and depletion transistors with 0.3Mym gate length. First results show a data rate of over 20 Gbit/s at 5 V supply voltage and 250 mW power consumption. The output voltage swing is adjustable between 0.3 V and 0.8 V for a 50 Ohm load. The output level can be varied between plus1 V an minus1 V. Comparison between simulation and measurement shows very good agreement.

: http://publica.fraunhofer.de/dokumente/PX-2872.html