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20 Gb/s monolithic integrated clock recovery and data decision

Monolithisch integrierte Taktrückgewinnung und Datenregeneration

Pfleiderer, H.-J.:
ESSCIRC '94. 20th European Solid State Circuits Conference. Proceedings
Gif-sur-Yvette: Editions Frontieres, 1994
ISBN: 2-86332-160-9
European Solid State Circuits Conference <20, 1994, Ulm>
Fraunhofer IAF ()
circuit techniques; clock recovery; data decision; Datenregeneration; optical data transmission; optische Daten-Übertragung; Schaltungstechnik; Taktrückgewinnung

An IC for 20 Gb/s clock recovery and data decision was realised using 0.3 micrometers gate-length QW-HEMTs. A narrow-band regenerative frequency divider with on-chip resonator filters is used for the clock recovery. The parallel processing concept is accepted for the data decision. The complex IC was tested on wafer using 5 and 10-Gb/s input data. The desired 10-GHz clock signal and regenerated data signals have been obtained. The 2x2 mm (exp 2) IC has a power consumption of about 0.5 W at -3 volt supply voltage.