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10 Gb/s single-chip data regeneration with an injection

Synchronised ring oscillator and an automatic phase adjustment
10 Gb/s Einchipdatenregenerator mit injektionssynchronisiertem Ringoszillator und automatischer Phasenjustierung

Grünbacher, H.:
ESSCIRC '97. Proceedings of the 23rd European Solid State Circuits Conference
Gif-sur-Yvette: Ed. Frontieres, 1997
ISBN: 2-86332-220-6
European Solid State Circuits Conference (ESSCIRC) <23, 1997, Southampton>
Fraunhofer IAF ()
clock recovery; data decision; Datenentscheider; GaAs HEMT; Taktrückgewinnung

A new concept of high-speed data regeneration was developed by using an injection-synchronised narrowband ring oscillator for the clock recovery and an automatic phase adjusting loop for the optimum data decision. A single-chip data regeneration IC has been realised by using our 0.3 mu m gate-length QW-HEMT GaAs technology and characterised on-wafer at STM-64 level (~10 Gb/s) of the SDH-standard. Even with a 100 mV, jittered input data signal, high-quality clock and data signals were regenerated. The recovered clock has an amplitude of 280 mV, a rms time jitter of 2.5 ps, and a phase noise of -88.5 dBc/Hz at 10 kHz offset. The regenerated data show fully open eyes with a height of >200 mV. The 1.5 x l.5 mm2 IC can be operated with a single supply voltage of -3V with a dc consumption of about 300 mW.