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Performance issues of SOI CMOS circuits at low supply voltages

: Abel, H.B.; Zimmer, G.


Maszara, W. ; Institute of Electrical and Electronics Engineers -IEEE-:
International SOI Conference '93. Proceedings
New York/N.Y.; Piscataway/N.J., 1993
ISBN: 0-7803-1346-1
S.104-105 : Lit.
International SOI Conference <1993, Palm Springs/Calif.>
Fraunhofer IMS ()
circuit simulation; low voltage; Niederspannung; Schaltungssimulation; SOI-CMOS

The SPICE implementation of our previously presented charge sheet model of the SOI MOSFET has been used to investigate the performance of SOI CMOS circuits at typical battery voltages (1.35...1.55V). In comparison to conventional CMOS circuits, speed gains of more than 50 percent have been found, which is mainly due to the small parasitic capacitances and reduced short channel effects.