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7.5 Gb/s monolithically integrated clock recovery circuit using PLL and 0.3 micro-meter gate length well HEMTs

7.5 Gb/s monolitisch integrierte Schaltung zur Taktrückgewinnung mit einem PLL und 0.3 micro-meter Gatelängen Qauntum Well HEMTs
 

IEEE journal of solid-state circuits 29 (1994), Nr.8, S.995-997 : Abb.,Lit.
ISSN: 0018-9200
Englisch
Zeitschriftenaufsatz
Fraunhofer IAF ()
circuit technology; clock recovery; integrated circuit; integrierte Schaltung; optical data transmission; optische Datenübertragung; Schaltungstechnik; Taktrückgewinnung

Abstract
A monolithically integrated clock recovery (CR) circuit making use of the phase-locked loop (PLL) circuit technique and enhancement/depletion AlGaAs/GaAs quantum well-high electron mobility transistors (QW-HEMT's) with gate lengths of 0.3 mym has been realized. A novel preprocessing circuit was used. In the PLL a fully-balanced varactorless VCO was applied. The VCO has a center oscillating frequency of about 7.7 GHz and a tuning range greater than 500 MHz. A satisfactory clock signal has been obtained at a bit rate of about 7.5 Gb/s. The power consumption is less than 200 mW at a supply voltage of -5 V.

: http://publica.fraunhofer.de/dokumente/PX-2813.html