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A parallel neural network emulator based on application-specific VLSI communication chips

: Schwarz, M.; Hosticka, B.J.; Kesper, M.; Scholles, M.


International Conference on Microelectronics for Neural Networks and Fuzzy Systems 1994
Los Alamitos: IEEE Computer Society Press, 1994
ISBN: 0-8186-6710-9
International Conference on Microelectronics for Neural Networks and Fuzzy Systems <4, 1994, Turin>
Fraunhofer IMS ()
adaption; adaptive signal processing; anwenderspezifische integrierte Schaltung; ASIC; Biokybernetik; biological cybernetics; biological neural network; Echtzeitbetrieb; Emulation; hardware; neural emulator; neural hardware; neuronales Netzwerk; parallel computers; Parallelrechnersystem; real-time systems; Signalverzögerung; system design; Systementwurf

This work describes a parallel neural network emulator which combines use of application-specific VLSI communication processors and standard DSPs as programmable processing elements. Locally interconnected communication processors attached to each DSP can span up 2D- or 3D-grids containing large number of computing nodes and thus form highly parallel multiprocessor networks capable of global pipelined packet switched routing. The use of standard DPSs as processing element enables the emulation of different types of neurons. These include biologically inspired models with learnable synaptic weights and delays, variable neuron gain, and static and dynamic thresholding. We describe applications of the emulator that include neural robot control as well as temporal signal processing, e. g. beamforming.