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A 3.6 Gigasample/s 5 bit analog to digital converter using 0.3 mu m AlGaAs-HEMT technology



Institute of Electrical and Electronics Engineers -IEEE-:
15th Annual GaAs IC Symposium 1993. Technical Digest
New York/N.Y.: IEEE, 1993
ISBN: 0-7803-1393-3
ISBN: 0-7803-1394-1
ISBN: 0-7803-1395-X
GaAs IC Symposium <15, 1993, San Jose/Calif.>
Fraunhofer IIS A ( IIS) ()
comparator; flash ADC; Gallium Arsenid; gallium arsenide; HEMT; Komparator; Parallelumsetzer

A 0.3 mu m AlGaAs-HEMT technology was used to develop a high speed Analog to Digital Converter (ADC). The 5 bit converter based on a parallel architecture, operates up to a 3.6 GHz sampling rate. Excellent dynamic performance was achieved by an optimized comparator design and careful layout of the signal and clock lines. Each comparator is preceeded by a preamplifier to enhance its sensitivity and to minimize clock kickback. Using source follower buffers at the input, a very linear input capacitance was achieved. Thus the ADC's overall input capacitance is voltage independant.