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A 1.90 GBit/s monolithic comparator implemented on an analog bipolar array

: Cepl, F.; Sauerer, J.; Hagelauer, R.; Seitzer, D.

DOI: 10.1109/BIPOL.1990.171123

	Jopke, J.V. ; Institute of Electrical and Electronics Engineers -IEEE-: Bipolar Circuits and Technology Meeting 1990. Proceedings New York, NY: IEEE, 1990 S.48-51
	Bipolar Circuits and Technology Meeting <1990, Minneapolis>

	Englisch
	Konferenzbeitrag
	Fraunhofer IIS A ( IIS) ()

Abstract
A monolithic comparator with sample rates up to 1.9 Bbit/s integrated on an analog array is presented. The circuit has been implemented on an analog array in a standard bipolar process (fT, NPN = 6.5 GHz). A parallel circuit structure doubles maximum sampling rate.