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An 1.5 V cyclic A/D converter CMOS technology

 

Garda, P.:
ESSCIRC '95. 21th European Solid State Circuits Conference. Proceedings
Gif-sur-Yvette: Editions Frontieres, 1995
ISBN: 2-86332-180-3
S.142-145
European Solid State Circuits Conference <21, 1995, Lille>
Englisch
Konferenzbeitrag
Fraunhofer IMS ()
Analog-Digital-Umsetzung; CMOS-Technik; low voltage; SC-circuit

Abstract
A low-cost 1.5 V A/D converter has been realized in standard CMOS technology. It combines low-voltage switched-capacitor technique with a differential signal path. The conversion is programmable and insensitive to the capacitor ratio and the amplifier offset voltage. A complete n-bit conversion needs 3n clock cycles. The chip area is 4 mm2 in a 1.5 micro-m CMOS technology with treshold of 0.8 V.

: http://publica.fraunhofer.de/dokumente/PX-2709.html