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MultiGbits/s data regeneration and clock recovery IC design.

IC-Entwurf für Multi-Gbit/s Datenregeneration und Taktrückgewinnung
 
: Wang, Z.

Annales des telecommunications 48 (1993), Nr.3/4, S.132-147
ISSN: 0003-4347
ISSN: 1958-9395
Englisch
Zeitschriftenaufsatz
Fraunhofer IAF ()
circuit design; digital signal; digital transmission; digitale Transmission; digitales Signal; fast circuit; phase-locked loop; Phasenregelungskreis; rapid transmission; regenerator; Schaltungsentwurf; schnelle Schaltung; schnelle Transmission; Taktrückgewinnung; timing recovery; transmission equipment; transmission performance; Transmissionsapparat; Transmissionseigenschaft

Abstract
A regenerative data transmission system is briefly outlined. Some important aspects related to the data regeneration and the clock recovery, such as the forms, the spectra, the jitter and the measurements of the data and clock signal, are summarized. The principle and the IC realisation of DR is discussed. Optimal CR circuits are deduced. Its preprocessing part and three categories of the main processing part, i.e., with a passive filter, with a narrowband regenerative frequency divider and with a phase- locked loop, are studied in detail. All circuits discussed are designed for applications in multibit/s optical transmission systems, and are mainly based on high-speed Si bipolar technologies.

: http://publica.fraunhofer.de/dokumente/PX-25259.html