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Measurement of PbSn and AuSn flip chip area bump thermal resistance

: Hahn, R.; Kamp, A.; Reichl, H.

Zakel, E.; Oppermann, H. ; Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration -IZM-, Berlin:
Area array packaging technologies
Berlin: IZM, 1997
Workshop on Flip Chip, CSP and Ball Grid Arrays <2, 1997, Berlin>
Fraunhofer IZM ()
ageing; cooling; flip-chip devices; gold alloys; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; lead alloys; microassembling; Modules; Soldering; thermal resistance; tin alloys

Summary form only given. The thermal management of electronic packages has become increasingly important due to the trends towards higher packaging density and power dissipation. For specific high frequency applications, GaAs devices and MMICs are flip chip interconnected to improve electrical and thermal performance. Here, the flip chip bumps represent the only heat transfer path. The objective of this investigation was twofold: (1) to provide reliable data for the thermal resistance of flip chip area bonds, which is required for the design of electronic modules; and (2) to analyze the influence of materials selection, solder thickness, aging and reliability testing on the thermal resistance of flip chip bonds.