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1988
Conference Paper
Titel
Low noise - low power CMOS readout system for silicon strip detectors
Abstract
Two readout systems for silicon strip detectors (128- and 64-channels) have been developed in CMOS technology. The readout systems have been designed for a readout pitch of 50 mym and 100 mym, respectively. They provide signal amplification, noise flitering, parallel storage, and serial readout and contain a digital control for analog switching. Switched-capacitor filters are used in all channels for noise reduction by multi-correlated double sampling. Power consumption is controlled by an external reference voltage thus allowing for optimization of speed and noise behaviour versus power consumption for individual use in experiments. Power-down mode for further reduction of power dissipation is available without switching off the supply voltages. A high charge amplification (15mV/fC) and a good noise performance (335 ENC+ 30 ENC/pf) have been obtained at very low power consuption of 2mW per channel.