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A low latency time CORDIC algorithm with increased parallelism

: Hahn, H.; Hosticka, B.J.; Timmermann, D.

IEEE transactions on computers 41 (1992), Nr.8, S.1010-1015
ISSN: 0018-9340
International Symposium on Circuits and Systems (ISCAS) <24, 1991, Singapore>
Fraunhofer IMS ()
Algorithmen; algorithms; computer arithmetic; CORDIC; Parallelismus; Rechnerarchitektur

In this contribution we present several methods for increasing the speed of the CORDIC algorithm. First we develop an improved method which guarantees a constant scale factor when employing redundant addition schemes. Then an architecture with increased parallelism will be described which considerably reduces, in theory and practice, the CORDIC latency time with a reduced amount of hardware.