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A low latency time CORDIC algorithm with increased parallelism

: Hahn, H.; Hosticka, B.J.; Timmermann, D.

Institute of Electrical and Electronics Engineers -IEEE-:
IEEE International Symposium on Circuits and Systems 1991. Final program
New York/N.Y., 1991
International Symposium on Circuits and Systems (ISCAS) <24, 1991, Singapore>
Fraunhofer IMS ()
algorithms; computer arithmetic; CORDIC

In this contribution we present several methods for increasing the speed of the CORDIC algorithm. First we develop an improved method which guarantees a constant scale factor when employing redundant addition schemes. Then an architecture with increased parallelism will be described which considerably reduces, in theory and practice, the CORDIC latency time with a reduced amount of hardware.