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An interpreter for general netlist design rule checking

 
: Pelz, G.DT Conference

:

Design Automation Conference. Proceedings
Los Alamitos: Computer Society Press, 1992
ISBN: 0-8186-2822-7
S.305-310
Design Automation Conference <29, 1992, Anaheim/Calif.>
Englisch
Konferenzbeitrag
Fraunhofer IMS ()
circuit CAD; electrical design rules; elektrische Entwurfsregel; interpreter; Interpretierer; Mengenlehre; netlist design; Netzlistenprüfung; Rechnerunterstützer Schaltungsentwurf; rule check; set theory; testability rules; Testbarkeitsregeln

Abstract
A new approach to general netlist design rule checking is presented, which has been successfully applied to design for testability (DFT) rule checking and electrical rule checking. Core of the checker is an interpreter, which performs operations of a set-based calculus. In combination with hierarchy preprocessing by expansion and netlist pattern matching, the interpreter approach turned out to be flexible and efficient.

: http://publica.fraunhofer.de/dokumente/PX-19820.html