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1989
Conference Paper
Titel
Field isolation using shallow trenches for submicron CMOS technology
Abstract
This paper presents a shallow trench isolation technique using plasma etching, LPCVD oxide fill, and planarization. This novel planarization technique applying X-ray lithography and isotropic O2-plasma etch needs no additional mask for block resist patterning over large isolation areas. MOSFETs have been fabricated showing nearly zero channel width loss and no treshold voltage shift to 0.8 mym channel width.