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Analytical model of short-channel gate enclosed transistors using Green functions

 
: Lopez-Martinez, P.; Hauer, J.; Blanco-Filgueira, B.; Cabello, D.

:

Solid-State Electronics 53 (2009), Nr.5, S.514-519
ISSN: 0038-1101
Englisch
Zeitschriftenaufsatz
Fraunhofer IIS ()

Abstract
Enclosed-layout transistors fabricated in standard CMOS processes are known to offer a natural robustness against radiation effects, a characteristic which is boosted in submicron technologies due to the reduction of the oxide thickness. In this paper, a thorough analytical I-V model of short-channel polygonal enclosed-layout transistors is proposed, addressing the issues of drain-induced barrier lowering and threshold voltage roll-off due to short-channel effects. Experimental data is reported, showing good agreement with the theoretical model.

: http://publica.fraunhofer.de/dokumente/N-96117.html