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UV nanoimprint lithography process optimization for electron device manufacturing on nanosized scale

: Schmitt, H.; Amon, B.; Beuer, S.; Petersen, S.; Rommel, M.; Bauer, A.J.; Ryssel, H.

Preprint urn:nbn:de:0011-n-956846 (250 KByte PDF)
MD5 Fingerprint: e3e78508a39771906d35f04d742fe884
Erstellt am: 9.9.2010

Raptis, I.:
34th International Conference on Micro- and Nano-Engineering, MNE 2008 : September 15 - 18, 2008, Athens, Greece
Amsterdam: Elsevier, 2009 (Microelectronic engineering 86.2009, Nr.4-6)
ISSN: 0167-9317
International Conference on Micro- and Nano-Engineering (MNE) <34, 2008, Athens>
Konferenzbeitrag, Zeitschriftenaufsatz, Elektronische Publikation
Fraunhofer IISB ()
UV nanoimprint lithography; residual layer thickness; UV polymer; etch resistance; electron device; MOSFET

Imprint specific process parameters like the residual layer thickness and the etch resistance of the UV polymers for the substrate etch process have to be optimized to introduce UV nanoimprint lithography (UV NIL) as a high-resolution, low-cost patterning technique for research and industry into electron device manufacturing. Additionally, UV NIL processes have to be compatible with conventional silicon (Si) semiconductor processing. Within this work, the minimization of the residual layer thickness by using a multi-drop ink-jet system, which was integrated into the imprint stepper NPS300 from S-E-T (formerly SUSS MicroTec), in combination with a low viscous UV polymer from Asahi Glass Company is shown. The etch resistance of different UV polymers against the poly-Si etch process was incr eased by 50% with an appropriate post-exposure bake. A poly-Si dry etch process was used to pattern the gates of short channel MOSFETs. After optimizing the poly-Si etch, properly working short channel MOSFETs with a minimum gate length of about 90 nm were fabricated demonstrating successfully the compatibility of UV NIL with conventional Si semiconductor processing on nanosized scale.