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Design of reliable circuits by determination of SOA borders as part of the degradation analysis

 
: Jancke, R.; Ellmers, C.; Gaertner, R.

Semiconductor Conference 2009. CD-ROM : Chip, Packaging, Design, Simulation and Test; International Conference, Workshop and Table-top Exhibition
Martinsried: Gerotron Communication, 2009
4 S.
Semiconductor Conference <2009, Dresden>
Englisch
Konferenzbeitrag
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
reliability; degradation; aging; safe operating area; design support

Abstract
Analysis of device degradation based on stress experiments is part the process qualification. The impact of these aged devices on circuit behavior can be explored in simulation if equivalent aging models of degradation mechanisms are available and the individual stress at each device is determined. In this paper hot carrier lifetime degradation is considered and appropriate aging models are used as part of an aging simulation flow. In addition the aging models are used to compute SOA (safe operating area) diagrams that allow finding the reasons for premature degradation. The presented analysis methods support design verification to ensure robustness and reliability of the produced circuit.

: http://publica.fraunhofer.de/dokumente/N-95567.html