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Technologies for 3D wafer level heterogeneous integration

 
: Wolf, M.J.; Ramm, P.; Klumpp, A.; Reichl, H.

:

Design, Test, Integration and Packaging of MEMS/MOEMS : Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS; 9-11 April 2008, Nice, France
Grenoble: CMP, 2008
ISBN: 978-2-35500-006-5
S.123-126
Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP) <2008, Nice>
Englisch
Konferenzbeitrag
Fraunhofer IZM ()

Abstract
3D integration is a fast growing field that encompasses different types of technologies. The paper addresses one of the most promising technology which uses Through Silicon Vias (TSV) for interconnecting stacked devices on wafer level to perform high density interconnects with a good electrical performance at the smallest form factor for 3D architectures. Fraunhofer IZM has developed a post front-end 3D integration process which allows stacking of functional and tested FE-devices e.g. sensors, ASICs on wafer level as well as a technology portfolio for passive silicon interposer with redistribution layers and TSV.

: http://publica.fraunhofer.de/dokumente/N-93869.html