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A dc I-V model for short-channel polygonal enclosed-layout transistors

: Lopez-Martinez, P.; Hauer, J.; Blanco-Filgueira, B.; Cabello, D.


International journal of circuit theory and applications 37 (2009), Nr.2, S.163-177
ISSN: 0098-9886
ISSN: 1097-007X
European Conference on Circuit Theory and Design (ECCTD) <18, 2007, Sevilla>
Zeitschriftenaufsatz, Konferenzbeitrag
Fraunhofer IIS ()

Despite the demonstrated radiation immunity of gate-enclosed layout transistors in deep submicron CMOS technologies, there is a significant lack of a thorough theoretical study addressing fundamental design issues on this kind of transistors. In this paper we propose a physical dc I-V model for short-channel polygonal-shape enclosed-layout transistors in both the linear and saturation regions of operation accounting for second-order effects such as depletion region non-uniformity, carrier velocity and channel length modulation. The impact of this layout style on the driving capability of the devices is also investigated. Experimental results based upon a fabricated NMOS test chip containing these devices in a standard 0.18 mu m CMOS technology process are presented. The comparison of the theoretical prediction with the experimental data show close agreement.