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CMOS compatible through wafer interconnects for medical imaging detectors

: Vogtmeier, G.; Drabe, C.; Dorscheid, R.; Steadman, R.; Jeroch, W.


Yu, B. ; Institute of Electrical and Electronics Engineers -IEEE-:
IEEE Nuclear Science Symposium conference record, NSS 2007. Vol.5 : Nuclear Science Symposium and Medical Imaging Conference; Honolulu, HI, 26 October - 3 November 2007
Piscataway/NJ: IEEE, 2007
ISBN: 1-4244-0922-5
ISBN: 978-1-4244-0922-8
Nuclear Science Symposium (NSS) <2007, Honolulu/Hawaii>
Medical Imaging Conference (MIC) <2007, Honolulu/Hawaii>
Fraunhofer IPMS ()

Modern medical imaging systems like Computed Tomography (CT) require advanced technologies for the imaging sensor and processing electronics as well as for the packaging technologies [1] to build an integrated sensor-system. As the size of the overall detector increased within the last years, new solutions for the realization of these large area detectors are required especially for advanced systems with integrated detector electronics. As the pixel size is about 1.1 x 1.4 mm² the overall size of the detector, with about 60,000 pixels, is in the range of 76,000 mm². Several advanced concepts - realized in standard CMOS technology - for active pixel arrays with chargeintegration [2], high dynamic range current amplifier [3] and inpixel sigma-delta-modulator [4] have been investigated. For the usage in large area detectors new packaging concepts have to be developed as a four-side-buttable (tile) structure can only be realized with a backside connection of the chip. In our development the Through Wafer Interconnects (TWI) do not necessarily show up in the front side as metal signal layers could be used for signal routing on top of the TWI. From CT application the geometric and the electric specifications for the TWI have been derived. The optical sensitive front-side of the chip that is attached to a scintillator crystal is not influenced by the processing of the TWI. The basic idea for the CMOScompatible TWI technology is the design of interconnecting conductive trench geometries in the wafer prior to the CMOS processing.