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Semi-formal verification of the steady state behavior of mixed-signal circuits by SAT-based property checking

: Schönherr, J.; Freibothe, M.; Straube, B.; Bormann, J.


Margaria, T.:
International Symposium on Leveraging Applications of Formal Methods, ISoLA 2004. Revised selected papers : Paphos, Cyprus, October 30 - November 2, 2004
Amsterdam: Elsevier, 2008 (Theoretical computer science 404.2008, Nr.3)
ISSN: 0304-3975
International Symposium on Leveraging Applications of Formal Methods (ISoLA) <1, 2004, Paphos>
Konferenzbeitrag, Zeitschriftenaufsatz
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

In this article, a verification methodology for mixed-signal Circuits is presented that can easily be integrated into industrial design flows. The proposed verification methodology is based on formal verification methods. A VHDL behavioral description of a mixed-signal circuit is transformed into a discrete model and then verified using well-established tools from formal digital verification. Using the presented methodology, a much higher coverage of the functionality of a mixed-signal circuit can be achieved than with simulation based verification methods. The approach has already been successfully applied to industrial mixed-signal circuits.