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SHAPES - A scalable parallel HW/SW architecture applied to wave field synthesis

SHAPES - eine skalierbare parallele HW/SW-Architektur für die Wellenfeldsynthese
: Sporer, T.; Beckinger, M.; Franck, A.; Bacivarov, I.; Haid, W.; Huang, K.; Thiele, L.; Paolucci, P.S.; Bazzana, P.; Vicini, P.; Ceng, J.; Kraemer, S.; Leupers, R.

Pedersen, J.A. ; Audio Engineering Society -AES-:
DSP for loudspeakers : The proceedings of the AES 32nd international conference. 2007 September 21 - 23, Hillerød, Copenhagen, Denmark
New York, NY: AES, 2007
ISBN: 978-0-937803-60-8
Audio Engineering Society (International Conference) <32, 2007, Copenhagen>
Fraunhofer IDMT ()
Audiosignal; Parallelverarbeitung; digitaler Signalprozessor; Mehrprozessorbetrieb; Schallquelle; Regelalgorithmus; Laufzeitentzerrung; Modellsimulation; Schallfeld

The usage of advanced audio processing algorithms in products has always been limited by the available processing power. For powerful concepts like the wave field synthesis (WFS) the performance is limited by the execution speed. In the past it was possible to increase the performance of digital signal processors by increasing the clock rate. The next generation will be highly parallel heterogeneous multi-processor systems. This paper presents a new parallel processor architecture and the first steps towards an adequate optimization of WFS. A software development environment which assists in creating scalable programs for highly parallel hardware will be further explained. An enhanced WFS convolution structure is presented which use position dependent filtering and improve the interpolation necessary for moving sound sources. Several algorithmic blocks of Wave Field Synthesis, which are essential for WFS in real world applications, have been analysed in respect to parallelisation and implementation on that hardware. This includes a new approach for delay interpolation for moving sound sources in WFS. The new scheme provides an artefact reduced, highly parallelized, algorithm for moving sound sources. A first implementation of some blocks of these algorithms was simulated in the VSP simulator.
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