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A system on a chip architecture of an H.264/AVC coprocessor for DVB-H and DMB applications

: Stabernack, B.; Wels, K.-I.; Hubert, H.


IEEE transactions on consumer electronics 53 (2007), Nr.4, S.1529-1536
ISSN: 0018-9308
ISSN: 0098-3063
Fraunhofer HHI ()
system on chip; video coding

The new DVB-H standard allows broadcasting of audio/video content to mobile terminals. Such devices underlie severe restrictions concerning processing load and power consumption. The most computational intensive and therewith most power consuming part of such terminals is the decoding of the H.264/AVC video datastream. We present optimization strategies for software-based H.264/AVC video decoding as well as the architecture of an H.264/AVC decoding companion chip with specialized coprocessors, which targets the above mentioned restrictions.