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2007
Conference Paper
Titel
CMOS Silicon-on-Insulator technology: An alternative for NIR quantum efficiency enhanced CMOS imaging pixel detectors
Abstract
An experimental comparison between Time-Compression (TC) photogate pixel detectors fabricated in both, Silicon-on-Insulator (SOI) CMOS and 0.5µm standard CMOS processes, respectively, are presented to illustrate the convencience of using separated detection and readout regions integrated on a same CMOS imaging pixel.