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RISC-V based SoC with integrated switched-capacitor PUF in 180 nm

 
: Müller, Kai-Uwe; Stanitzki, Alexander; Fedtschenko, Tatjana; Kokozinski, Rainer

MikroSystemTechnik Kongress 2021 : Mikroelektronik/ Mikrosystemtechnik und ihre Anwendungen. Innovative Produkte für zukunftsfähige Märkte, 08. - 10. November 2021, Stuttgart-Ludwigsburg
Berlin: VDE-Verlag, 2021
ISBN: 978-3-8007-5656-8 (CD-ROM)
ISBN: 3-8007-5656-0 (CD-ROM)
S.657-659
MikroSystemTechnik Kongress <2021, Ludwigsburg>
Deutsche Forschungsgemeinschaft DFG
IGF; 20690 N
Sichere Elektronik für die digitalisierte und vernetzte Produktion
Englisch
Konferenzbeitrag
Fraunhofer IMS ()
RISC-V; physically unclonable functions (PUF); hardware security

Abstract
The RISC-V Instruction Set Architecture (ISA) as an open standard is a good alternative to proprietary RISC architectures with high license costs which can be problematic for smaller companies. Physical Unclonable Functions (PUF) are a promising way to build secure key storage for authentication and encryption purposes. The paper describes a reference System-on-a-Chip (SoC) design for use with a wide variety of different sensor applications as well as different wired or wireless communication interfaces and an integrated PUF, controlled by a RISC-V processor.

: http://publica.fraunhofer.de/dokumente/N-645388.html