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2021
Conference Paper
Titel
Simulating large neural networks embedding MLC RRAM as weight storage considering device variations
Abstract
In this paper we present a method to evaluate the behavior of neuronal network (NN) architectures, concerning the error rate of RRAM devices used as weight storage, relative to fabrication variances. While the behavior of non-ideal RRAM devices can cause system failures (e.g. due to bit flips) in traditional computer architectures, NN exhibit inherent redundancy which makes these applications more tolerant against device variabilities. Therefore, we analyze the fabrication variances of RRAM cells which are used as weight storage in systolic array-based NN architectures, and bring these device level properties to the system level to show, if and how a NN application will be affected. Previous works were based on Mixed Signal simulations and lack the needed throughput to be able to evaluate nets of meaningful size. Our approach uses modern neural network libraries along with an abstraction of the device properties and can thus run five to six orders of magnitudes faster c ompared to the results of a traditional approach.