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SystemVerilog for Verification

Vortragsfolien des Webinars, July 7, 2021
: Pachiana, Gabriel

Dresden: Fraunhofer IIS, EAS, 2021
Webinar "SystemVerilog for Verification" <2021, Online>
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
Anfrage beim Institut / Available on request from the institute

Nowadays the increasing complexity in the electronic industry is not only driven by larger designs but also by the new layers of design requirements, like security requirements and safety requirements. These new challenges in modern IC/ASIC and FPGA projects also impacts functional verification effort and effectiveness. SystemVerilog is a language widely used for IC/ASIC and FPGA verification. Its verification features allow design and verification engineers to build testbenches and adopt key verification technologies (i.e. constrained random stimulus, functional coverage and assertions) to find functional flaws and mitigate its scape into production. This webinar gives you an introduction to the main SystemVerilog verification features, including classes, constrained random stimulus, coverage, assertions, and learn how to utilize these for more effective and efficient verification.