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PCB layout tool integrated loss and inductance estimation

: Hoffmann, S.; Hoene, E.; Schroeder, B.; Stube, B.; Alraai, A.; Moritz, O.; Müller, O.

Verband Deutscher Elektrotechniker e.V. -VDE-, Berlin:
CIPS 2020, 11th International Conference on Integrated Power Electronics Systems. Proceedings : March, 24 - 26, 2020, Berlin, Germany; CD-ROM
Berlin: VDE-Verlag, 2020 (ETG-Fachbericht 161)
ISBN: 978-3-8007-5225-6
ISBN: 978-3-8007-5226-3
ISBN: 3-8007-5225-5
International Conference on Integrated Power Electronics Systems (CIPS) <11, 2020, Berlin>
Fraunhofer IZM ()

This paper presents the implementation of the online inductance, loss and temperature distribution calculation integrated in a PCB layout tool. The parasitic inductances of certain current loops selected by the user are calculated with an existing PEEC solver. The developed add-on generates the 3D model automatically, activate the solver and extract the computation results. The loss solver implemented in the add-on calculates the losses and the temperature distribution according to a previously assigned current. As a result, the PCB layout designer is already efficiently supported during the design process. The method is validated using simulations and measurements of typical assemblies.