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Challenges of monolithic MEMS-on-CMOS integration for spatial light modulators

 
: Hohle, C.; Döring, S.; Friedrichs, M.; Gehner, A.; Rudloff, D.; Schulze, M.; Stübner, R.; Trenkler, D.

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Zappe, H. ; Society of Photo-Optical Instrumentation Engineers -SPIE-, Bellingham/Wash.:
MOEMS and Miniaturized Systems XX : 6-12 March 2021, Online Only, California, United States
Bellingham, WA: SPIE, 2021
Paper 116970V, 10 S.
Conference "MOEMS and Miniaturized Systems" <20, 2021, Online>
Englisch
Konferenzbeitrag
Fraunhofer IPMS ()

Abstract
The development of devices that are based on MEMS-on-CMOS technology becomes increasingly time-consuming since System-on-a-Chip (SoC) solutions for highly integrated and miniaturized devices are approaching smaller feature sizes. In order to reduce the development costs and shorten the time-to-market periods, the combination of commercially available CMOS processes from foundries with the subsequent processing in a dedicated MEMS facility is beneficial. This concept offers the possibility to separate the different technological requirements of conventional CMOS manufacturing and MEMS actor processing, which may follow different design rules and process specifications. As a representative of the dedicated MEMS foundries, Fraunhofer IPMS performs surface micromachining on 200 mm wafers for a variety of MEMS devices, in particular for spatial light modulators (SLM). Over the past decade, much experience was gained in development activities for customer specific applications like micro mirror arrays. In this paper, we will discuss essential requirements and upcoming challenges for the monolithic integration of surface micro-machined optical MEMS on foundry-fabricated CMOS backplanes, as conventional (i-Line) lithography is approaching patterning limits. We will present approaches of tuning the planarization of the CMOS chip surface to achieve an excellent mirror array flatness with CMOS compatible inorganic sacrificial layer techniques. Concepts like Mix&Match lithography for achieving high overlay accuracy and the litho stitching technique for the patterning of large chips will be reviewed and a brief outline of our roadmap for the implementation of DUV lithography will be presented.

: http://publica.fraunhofer.de/dokumente/N-633370.html