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Analog Chip Layout: Creativity Vs. Deadlines

Redaktionell betreuter Blogbeitrag auf https://semiengineering.com, September 10th, 2020
 
: Prautsch, Benjamin

:
Volltext (HTML; )

Online im WWW, 2020
Englisch
Blogbeitrag, Elektronische Publikation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Abstract
On the tension between creative, precise high-end layouts and firmly established tapeout deadlines. The entire design of integrated circuits, from the specification onward, depends on successful validation by measurement of microchips. One key milestone in this process is the completion of the layout. However, the path to reach this point can be quite difficult as many iterations are usually required. It includes: • Iterations with the customer to finalize the specification. • Iterations between architecture and IP design or IP integration to comply with the specification. • Iterations in circuit design to find the right topology. • Iterations between circuit design and layout design to eliminate all parasitic effects, determine the appropriate sizing, and comply with area and quality requirements. This design flow is long, and it is not rare for a change to find its way into the layout “at the last minute.” This often results in frustration and errors just before tapeout. So are there ways to respond quickly and implement the required changes fast? Here are a few ideas.

: http://publica.fraunhofer.de/dokumente/N-633139.html