Fraunhofer-Gesellschaft

Publica

Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

Low-Noise Si-JFETs Enhanced by Split-Channel Concept

 
: Sturm-Rogon, Leonhard; Neumeier, Karl; Kutter, Christoph

:

IEEE transactions on electron devices 67 (2020), Nr.11, S.4789-4793
ISSN: 0018-9383
ISSN: 1557-9646
Bundesministerium für Bildung und Forschung BMBF (Deutschland)
FMD
Englisch
Zeitschriftenaufsatz
Fraunhofer EMFT ()
logic gates; JFET; resistance; transconductance; noise measurement; Junction

Abstract
We present the results of low-noise silicon junction field-effect transistors (JFET) with a split-channel concept. The device can be manufactured as a module in a standard CMOS process. The channel is split under the top gate of the JFET into a source-side main channel and a drain-side-extended drain channel. Devices with design gate length between 1.0 and 3.0 μm and effective channel length between 0.1 and 2.2 μm were fabricated. It is shown that transconductance and channel resistance are dominated by the overlap between the main channel and the top gate. Output resistance can be enhanced by increasing the overlap of the extended drain channel with the top gate. A cutoff frequency of up to 2.5 GHz, 60-mS/mm maximum transconductance, and an intrinsic gain of 2200 were achieved. For the main channel length below 1 μm, a strong roll-off behavior of the threshold voltage is observed. The flicker-corner frequency for 1/f noise is 500 Hz. Above 1 kHz, √ a value of 2.5-nV/ Hz input-referred voltage noise density at 0.3-pF input capacitance was achieved. Also, a brief comparison to devices from other publications is presented.

: http://publica.fraunhofer.de/dokumente/N-621908.html