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DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator

: Steiner, Lukas; Jung, Matthias; Prado, Felipe S.; Bykov, Kirill; Wehn, Norbert


Orailoglu, A.:
Embedded Computer Systems: Architectures, Modeling, and Simulation. 20th International Conference, SAMOS 2020. Proceedings : Samos, Greece, July 5 - 9, 2020
Cham: Springer, 2020 (Lecture Notes in Computer Science 12471)
ISBN: 978-3-030-60939-9
ISBN: 978-3-030-60938-2
ISBN: 978-3-030-60940-5
International Conference on Embedded Computer Systems - Architectures, Modeling, and Simulation (SAMOS) <20, 2020, Online>
Deutsche Forschungsgemeinschaft DFG
Fraunhofer IESE ()
DRAM ; Simulation ; SystemC ; TLM

The simulation of DRAMs (Dynamic Random Access Memories) on system level requires highly accurate models due to their complex timing and power behavior. However, conventional cycle-accurate DRAM models often become the bottleneck for the overall simulation speed. A promising alternative are DRAM simulation models based on Transaction Level Modeling, which can be fast and accurate at the same time. In this paper we present DRAMSys4.0, which is, to the best of our knowledge, the fastest cycle-accurate open-source DRAM simulator and has a large range of functionalities. DRAMSys4.0 includes a novel simulator architecture that enables a fast adaptation to new DRAM standards using a Domain Specific Language. We present optimization techniques to achieve a high simulation speed while maintaining full temporal accuracy. Finally, we provide a detailed survey and comparison of the most prominent cycle-accurate open-source DRAM simulators with regard to their supported features, analysis capabilities and simulation speed.