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Stress-induced transistor degradation studied by an indentation approach

: Schlipf, Simon; Clausner, André; Paul, Jens; Capecchi, Simone; Wambera, Laura; Meier, Karsten; Zschech, Ehrenfried


IEEE transactions on device and materials reliability 21 (2021), Nr.1, S.9-16
ISSN: 1530-4388
ISSN: 1558-2574
Fraunhofer IKTS ()
stress; transistor degradation; transistors; strain; silicon; geometry; degradation; logic gates; chip-packages interaction (CPI); finite element method (FEM); indentation; ring oscillator (RO); piezoresistive effect

The strain impact on integrated circuit performance is investigated by applying a novel indentation technique. The approach aims to investigate stress caused by CPI, particularly highly localized stress/strain with respect to the actual device geometry. Non-destructive elastic indentation is used to induce homogenous stress fields in the vicinity of the test structure by applying a contact with a spherical tip. Strain-sensitive ring oscillator structures manufactured in the 22 nm FDSOI CMOS technology node are designed to monitor the device and simultaneously the NMOS and PMOS strain behavior separately. Complementary FE-simulations provide a deeper insight into the obtained experimental results by transferring them from contact force into the stress/strain space and validating the indentation approach. Relevant layout and indentation dependent parameters are investigated and evaluated. The simulation of the strain induced mobility shift and the comparison with the established correlation verifies the accuracy of the approach. The results provide an insight into package-related stress and resulting transistor degradation, aiming at establishing a versatile tool to estimate the effect of specific real-usage conditions.