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Simulation challenges of warpage for wafer- and panel level packaging

 
: Dijk, M. van; Kuttler, S.; Rost, F.; Jeaschke, J.; Walter, H.; Wittler, O.; Braun, T.; Schneider-Ramelow, M.

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Institute of Electrical and Electronics Engineers -IEEE-:
21st International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2020 : 5-8 July 2020, Cracow, Poland, Virtual Event
Piscataway, NJ: IEEE, 2020
ISBN: 978-1-7281-6049-8
ISBN: 978-1-7281-6050-4
S.230-235
International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE) <21, 2020, Online>
Englisch
Konferenzbeitrag
Fraunhofer IZM ()

Abstract
Fan-out Wafer and panel level packaging is one of the latest trends in microelectronic packaging. Realizing System in Packages (SiP) by wafer- or panel-level packaging, using overmolding and redistribution layers, requires several processing steps which all lead to different stress states in the panel/wafer assembly. These stresses result in deformation of the panel/wafer, so called warpage. Keeping the warpage within limits is important as subsequent processing steps can fail if deformations are too large or at least influences the reliability of the final SiP.Many experimental results have shown that the deformation is mostly non-symmetrical, meaning that instead of a symmetrical - bowl shaped deformation - a tunnel shaped deformation occurs. The main focus of this study is on how to represent this non-symmetrical deformation with numerical simulations. Our results show that the release step of the temporary carrier, necessary to hold the dies and mold compound during the processing, has a strong influence on the warpage, and needs to be considered to represent the warpage correctly.

: http://publica.fraunhofer.de/dokumente/N-614631.html